Saturday, 28 January 2012

Automatically Generate Quartus Pinning From Altium

The task of entering the pin mappings between FPGA I/O pins and signal names is both tedious and prone to errors. FPGA's with 484 pins are pretty common and this is by no means the largest. Typically you will have schematic drawings which you will need to reference to find out which signals are assigned to which FPGA pins. There are rumours that Altium Designer can export pinning information auto-magically however the consensus seems to be that this only works if you use Altium software for both schematic capture and HDL design entry. Since most people use Quartus/Xillinx tools for FPGA development, this is of limited use.

Fortunately, Altium - and just about any other EDA - can reliable export a netlist of you circuit. With this netlist you can readily extract the information you need. That is, the signal name and the FPGA pin number. If you have assigned sensible net labels in your design, it should be possible to convert this netlist file into a tickle script file for use with Quartus. The simplest method of conversion is with VIM text editor

From experience, I've found it best to save your design in the MultiWire (.NET file) format. I'm sure other netlist formats will work but this is the only one I've had success with.

The steps to follow are detailed below:

Step 1:

Open the FPGA schematic sheet(s) in Altium

Step 2: 

Extract a MultiWire Netlist from Altium: Design > Netlist for Document > Multiwire

Step 3: 

Open the netlist file in VIM, You should see a file like the following:

0V                U2                            T1
0V                U2                           T22
1V8               R9                             1
2V5               PL2                            1
2V5               RP36                           2
2V5               RP36                           3
2V5               RP36                           4
3V3               R7                             2
3V3               R8                             2
AUX_IN            U2                            B1
AUXTEST           J1                            11
AUXTEST           TP11                           1
AUXTEST           U2                            D2
CFCD1#            U2                            C3 
Step 4: 

Remove all components except the FPGA. You will need to replace "U2" with your chosen designator:


Step 5: 

Remove GND, VREF, VCCIO nets (feel free to add more nets to the blacklist):


Step 6: 

Convert netlist format to Quartus tickle assignments:

0,$ s:\(\p\+\)\s\+\(U2\a*\)\s\+\(\u\+\d\+\).*:set_location_assignment\tPIN_\3\t-to\t\1

Step 7: 

Check for any reserved pins you might have missed. You can always add these to the blacklist for the next time you use the script.

I have wrapped all of these operations into a single vim function which you can paste into your vimrc file (if you're not sure where this is, type :echo $MYVIMRC).

" Netlist to Quartus tcl assignment file conversion
" Author: 
" Function: Net2Pin 
" Parameters:
" #1 designator : string : (FPGA) component designator e.g. "U2" or "IC4"
" (case sensitive)
function! Net2Pin(designator)
    "Delete all Nets which aren't connected to specified component designator 
    let pattern = '/^\p\+\s\+' . a:designator . '\s\+.*/d'
    execute  "g!" . pattern
    "Delete reserved pins i.e. those used for power/ground/config/jtag
    let pattern = '/^\(GND\|0V\|1V2\|2V5\|3V3\|FPGAMSEL\|FPGATCK\|FPGATDI\|FPGATDO\|FPGATMS\).*/d'
    execute "g" . pattern

    "Convert netlist format to Quartus tcl assignments
    let pattern = '\(\p\+\)\s\+\(' . a:designator . '.*\)\s\+\(\w\+\d\+\).*:set_location_assignment\tPIN_\3\t-to\t\1'
    execute '0,$ s:' . pattern

Once you have saved your changes and reloaded your vimrc file (:source $MYVIMRC) you will be able to call the function as follows:
:call Net2Pin("U2") 

Replace "U2" with whatever designator you used for the FPGA in the schematic. The output of this function for the above example is:

set_location_assignment PIN_B1 -to AUX_IN           
set_location_assignment PIN_D2 -to AUXTEST          
set_location_assignment PIN_C3 -to CFCD1#           

License: GNU GPL

References - An essential resource for understanding vim regular expressions

:help vim-script-intro - A great starting point for understanding vim scripting

1 comment:

beesnotincluded said...

I've updated the scripts in this post to stop partial designator matches from letting rouge components through.

For example, if FPGA was U2, previously the script would match U2 with U23. The updated script should not do this!

If you would like a breakdown of the regular expressions then please request it in the comments.