Saturday, 22 December 2012

Shoe Rack Mistakes


Shoe Rack Project Update

The development of my woodworking skills is best documented by the mistakes I've made along the way! I've learned more from this project than I ever expected. I designed the shoe rack to be constructed from standard lumber sizes available at the hardware store. The joints are all dowel joints which I thought would be pretty straightforward to make and great for hiding mistakes.



After cutting all the timber to what I thought was the right lengths, I set about marking and drilling the dowel holes. I used my new marking gauge which I think I've finally got used to using. For this kind of project where there are lots of repeated cuts and holes to mark it was invaluable. I could set the gauge once and mark out all the pieces in next to no time. I should have bought this before starting my box project.

At this stage of construction I realized my first mistake. Pick the right dowel size. I went to the local Busy Bee Tools shop and bought a tub of 8mm wooden dowels - thinking that they looked about right for the job. The problem is that most of the lumber used in this project is 1/2" think, which is 12.25mm. For an 8mm dowel with room for glue I need a 8.5mm hole. This means I have less than 2mm either side of the hole. When you factor in my error in marking and drilling, the hole can end up being less than 1mm from the edge of the wood. This might be acceptable if you are using a drill press, but if you are using a hand-held drill it is really easy to get tear out. In the future I will use dowels that are no more than 1/3 the width of the pieces being joined. For this project, I really should have screwed and glued these small pieces and used dowels for the outer frame only.

The second mistake was using the nominal wood thickness instead of the actual thickness when making the plans. I'm sure this will catch me out again, but its such an easy mistake to make.


The picture above shows one of the shelves after the glue up. The glueing process was made difficult because I drilled the dowel holes too tight. Without room for the glue to exit the joint, I had to use incredible pressure to force the dowel into the holes. On several occasions this pressure caused glue to seep through the grain perpendicular to the dowel!

Having  glued the pieces together, I discovered I didn't have a clamp long enough to hold the work-piece together. This didn't seem too important because I knew the dowels were tight enough. I set the pieces to one side to dry and came back to find one of the shelves had twisted by about 1/4in corner to corner. In future builds I will try to clamp the pieces flat. The lumber had been stored indoors for several weeks before starting the project, so I do not think the warping was a result of the wood not being stable. I suspect a combination of very tight dowels, insufficient clamping and stresses in the structure due to poor hole placement caused the frame to bend.


The warped shelf has caused the final structure to be slightly warped too!. The right, front-most leg in the picture below is higher than the other three by approximately 1/4". The good news is that my marking and drilling skills improved during the construction and the vertical pieces fit together well.

The top, front and back horizontal slats are missing because these are the pieces I cut too short, as a result of assuming that the width of the 1x3" boards used for the posts was 3".


The most useful outcome of this project will not be a shoe rack! It will the be experienced gained from making something that was supposed to be a shoe rack! The purposes of this critical blog post is to document my mistakes so I don't repeat them in the future. It has been a lot of fun getting to this stage and although the results are a little disappointing, with some more glue and a pneumatic pin-nailer, I hope to square this thing up. 

I will post an update after the nail gun massacre. The great thing about being part of a hackerspace is that there is no shortage of power tools ... and people eager to use them!

Box Completed!

Just need to give it some coats of shellac then we're done.

The plans I used can be downloaded from Fine Woodworking (PDF Link)


Thursday, 6 December 2012

Box now has lid

Slow progress this week because I'm suffering from some kind of Canadian strength flu. I cut the lid with a fat drill bit (forgot propped term) and a scroll saw with some help from the Dremmel. Lots of sanding to go yet.

Also my Sony Xperia has a shit auto focus which seems to focus on least interesting artifact in field of view so sorry

Wednesday, 28 November 2012

Box Project Update

A quick update on my first woodworking project - I'm quite excited that it actually looks like a box now, and isn't a million miles away from the picture on the project plans.


Here is the box mid glue-up:

Here is the box after gluing and with the lid positioned. It still has to sanded, finished, nailed and a handle cut into the lid, but it has taken me about 10 hours just to get to this point!





Sunday, 25 November 2012

Da Hood

We've just moved into our own place in Calgary and are enjoying getting to know the area. Yesterday the weather was beautiful so I went for a walk around the neighbourhood and took some photos as I went. Most of these photos were taken from Renfrew and Bridgeland, which are just north of down town Calgary.









Saturday, 24 November 2012

Sketchup Woodworking Plans

I used Sketchup today for the first time in order to plan a woodworking project. I'm trying to make a shoe rack to accommodate all of my shoes, yes both of them, and a tiny portion of my girlfriends collection.
I'm not going to disclose how long it took me to draw this. I found the online reference a bit lacking and struggled a lot with accurately positioning things but the end result is far better than I could have managed with a pen and paper. I've already bought the material and acquired most of the tools needed so I am eager to start making sawdust. In related news, I have joined a hackerspace in Calgary called Protospace. This is a great bunch of people who run a communal hacking-space with loads of tools and people who know how to use them. I'll blog more on this in the future.

Tuesday, 2 October 2012

The Seventh Day

My Girlfriend's Step-dad is on the verge of publishing his first novel. It's called "The Seventh Day" and it will be available on ebook from Amazon. For previews and details of the release date, check out his website:

http://ianshurville.com/



Friday, 7 September 2012

Camping in Bear Country

I've just returned from a short camping trip in Kananaskis and I cannot wait to go back. We stayed at a camp site called Sundance Lodges which has to be the best designed camp site I've ever stayed at. Being used to camping in Britain, the detail which most impressed me was how you could camp right next to your car/truck. The pitches were generously spaced and each one consisted of a metal fire pit, wooden picnic table, spacious pitch and a space to park your car/truck. The whole pitch was surrounded by the same dense forest which you'd find along  most of the trails in the area, so you could see chipmunks and squirrels rushing from tree to tree and under the Chevy. Being so close to your truck means you don't have to fill the tent porch with stuff you might need, because you can just leave it in the vehicle. The picture below was taken at dawn so the lighting wasn't great but you can see just how accommodating the site was:


From Camping in Kananaskis, 2012

What you cannot see from the picture is the camp-site office, or 'Trading Post', where you could buy everything you might have forgotten for your trip, not to mention pre-bundled firewood and gas lanterns to hire. Best of all, it was empty when we went during the middle of the week, right at the end of the summer.

The trails meandering across the Kananaskis landscape were spectacular. I cannot begin to imagine how much work is involved in keeping them clear of felled trees, wild plants, landslides and erosion from the melt water. It amused me to learn that most of the trails are used all year around, albeit on skis in the winter - since the walking trails double as excellent cross-country skiing. You would have to be a seriously good skier to tackle even the modest trails that we hiked, yet alone the trails deeper into the mountains.




The only thing missing from this camping trip was an OS map. Nothing compares to the reassuringly detailed, meticulously compiled and durable Ordnance Survey maps that you can buy in Britain. We found a very good contender which we brought with us, but they just don't compare. For anyone going walking Alberta, I can recommend Gem Trek Maps available here. Trails are clearly highlighted and even have the distances of the various stages marked above them. To be honest, for all of the trails we took, a map wasn't even necessary, since there were signs with maps and a 'you are here' pointer printed at every trail junction.






From Camping in Kananaskis, 2012


From Camping in Kananaskis, 2012

Monday, 20 August 2012

Big Move

It has taken 12 months of planning but I have finally emigrated to Canada. I landed four days ago at Calgary International Airport and after a brief interview with immigration staff I received my paperwork and was sent on my way to start a new life in Calgary.

I spent the nine long hours on the Airbus A330 learning a little about Canada, Alberta and Calgary. Before departing I downloaded the Wikibook of Canada. This is approx 220Mb of Canada related Wikipedia articles covering just about every area of general knowledge you could hope to learn. Of all the articles I read, the facts that stood out the most were:


  •  There are no rats in Alberta. This is because of a highly successful a mass extermination of the Norwegian Rat in the 1950s
  • In Canadian Federal politics, the funding of political parties is tightly controlled by legislation. Donations from private individuals is encouraged, whilst corporate donations are tightly restricted. Public funding is awarded to political parties based on previous and estimated proportions of the vote.
  • I've moved to the most Conservative province in Canada, Alberta, which has consistently elected a Conservative representative since the 70s
  • Alberta was one of the last provinces to join the confederation of Canada, only officially joining in 1905.
  • Income tax is 15% in the band $10k-$40k - a.w.e.s.o.m.e.

Things I've learned already that I didn't know before:
  • Mobile and Landline telephones do not display the number of the calling party by default. To get this information you have to pay extra for 'Caller ID' which not only shows the number but also the name -  even if they are not in your address book. 
  • You have to pay for nearly all banking services with the average charge being about $10/mo for a typical chequeing account.
  • Most banks have dual currency ATMs for accessing USD and CAD
  • Canoeing is a lot of fun
  • Most camping sites offer only gravel, concrete or generally hard pitches, since nearly everyone uses an RV for camping. Time for a better roll-mat
It's harvest time for hay crops and the machinery involved in felling, sweeping and bailing the hay is fascinating to watch. First the combine cuts it down. It sits drying in the field for a day, then a plough-like attachment sweeps it into a narrow channel. Finally the baler sweeps up the hay and compacts it into a bail. Periodically the hatch at the back of the baler opens and it poops out a great big bail of hay, already wrapped in plastic and twine. So readily amused am I that I photographed this happening and now have an album of pictures to show for it:



Monday, 2 July 2012

Time for a new log book

Some stats about my last log book:

To be fair, learned wisdom is pretty light compared to lead.

Wednesday, 20 June 2012

Who are Multicomp?

Today I learned that Multicomp, far from being an electronics manufacturer, are in fact a reseller of other manufacturer's components. Multicomp is owned by SPC Technologies, which in turn is owned by Premier Farnell. Presumably, Multicomp is an abbreviation of "Multiple Companies". Unsurprisingly, Farnell/Element 14/Newark stock Multicomp parts and, confusingly, list the manufacturer as 'Multicomp'.

I can't find any reliable source explaining what exactly Multicomp do, or what efforts they go to to control the quality of the products they resell, but the business probably works by purchasing large volumes of (presumably surplus) components from big manufacturers such as NXP, 3M, Fairchild etc. and then re-branding them as Multicomp parts. Multicomp is then offered as a value brand [1]. This includes re-formatting the datasheet to remove the OEM branding and replacing it with Multicomp/Farnell. Multicomp parts often sell for less than the identical part listed under the manufacturer's name.

I'm not really sure how this affects the decision to choose Multicomp components. On the one hand, Multicomp parts may be easier to source, cheaper and available in smaller MOQs; on the other hand, you don't really know who the manufacturer is or even if it will be the same manufacturer next month. Depending on the application, this might not be important, but I still feel that this arrangement could be better explained on the Farnell website.

Have you had good/bad experience with Multicomp components?

[1] http://uk.farnell.com/multicomp?isRedirect=true#
[2] http://www.mcmelectronics.com/content/en-US/about

Wednesday, 6 June 2012

When is CE not CE?

Answer: When it's a China Export !

Incredibly, some Chinese manufacturers are in the habit of applying a China Export mark to their electronic products which looks, at first glance, exactly the same as the European Conformity (CE) mark. Can you tell the difference?

The difference is most noticeable when you take your 'CE' marked product to an EMC test house, where you shouldn't be surprised if it fails at least one of the emissions or immunity tests.

This is exactly what happened to a colleague of mine.

Sources:
China Export on Wikipedia

Friday, 11 May 2012

DRUPA 2012 & Beckhoff XTS Linear Drive

I spent yesterday in Dusseldorf, Germany visiting DRUPA. DRUPA is is a quadrennial trade fair for the print media industry. DRUPA is massive. It must be the largest fair of its kind within the printing industry. As a certified geek, wandering around exhibition hall after exhibition hall of incredible machines and impressive engineering was just incredible. To give you an idea of the scale of the show, there is a daily newspaper dedicated to it. It is printed every day for the two week duration of the show. Exhibitors bring complete printing presses and media handling equipment. Big, noisy, fast, machines: Proper engineering. I watched an entire copy of Jane Eyre's Pride and Prejudice being printed in front of me in a matter of seconds!

One of the companies which fascinated me was Beckhoff.

Beckhoff are an automation company and specialise in PLCs, motor/servo controllers and IO modules. They were launching their eXtended Transport System (XTS). XTS is a modular linear driver motion system, which can be connected together to form circular transport systems for moving stuff around. I've embedded a video of the demonstration unit that I had the pleasure to watch yesterday. Whilst the science behind it is nothing new, the way it has been packaged and designed is very impressive.


Saturday, 28 April 2012

MIT 6.002x Midterm

Just completed the MIT6.002x Midterm exam with no mistakes. Good times.

MIT6.002x Midterm Celebration
MIT 6.002x Circuits and Electronics info

Good luck to those yet to complete it and/or putting it off.

Friday, 27 April 2012

Two Modelsim Tips You Should Know

Analogue Waveforms

Modelsim can display a signal in your VHDL/Verilog design as an analogue signal. One use for this is when you want to visualise the output of a digital to analogue converter to see if you have synthesised the waveform as you intended. To do this you can right-click on the signal name in the Wave window and select it's properties. Switch to the Format tab and select 'Analogue'. You can optionally set a maximum value for the signal so that Modelsim can stretch your waveform to fit the height of the row. For example, set it to 255 for an 8-bit DAC value.

Vi/Emacs Editor

You can tell Modelsim to use the key-bindings from your favourite editor (by which I mean Vi or Emacs). Do this by drilling down the Tools > Preferences > Text editor menus until you get to the option for switching from normal to Vi or Emacs key-bindings. The good news is it is slightly better than using normal mode. The bad news is, for Vi at least, many of the features are missing, probably because I'm used to using Vim. Search, file operations and the basic editing commands are all there, but it feels like an emulation rather than the real thing. My recommendation is to carry on using your favourite external editor by default and only use the Modelsim editor for minor changes.



Monday, 23 April 2012

Student Robotics 2012 was awesome

Saturday 14th and Sunday 15th of April saw the fifth annual Student Robotics competition. Thanks to the hard working 'Blue Shirts' the event was a great success! Every year the robots seem to get better and better and this year was no exception.

Here are some pictures of the SR2012 entrants which were stationary for long enough for me to photograph them! Not always a good quality in a robot!




The robot below belonged to my former secondary school, Bristol Grammar School. Unfortunately it was a bit pony. I'm sure next year they will be a force to be reckoned with:


'Aslam' was definitely the best dressed robot. Very well turned out.




Links:

ECS, Southampton
Student Robotics Website

Altium Designer Supplier Cost Rounding Error

Here's an annoying bug in Altium Designer Summer '09. Altium Designer allows you to link your schematic library components with a supplier's product inventory such as Digi-Key or Farnell. When you generate a BOM the supplier cost is retrieved from the supplier website and pumped into an Excel spreadsheet. Well that is the idea.

If you have components costing less than 1p and presumably 1 cent then they are rounded down to 0p. This is pretty unhelpful if you want to know the total BOM cost.

The workaround is to use the "Supplier Subtotal 1" field instead of "Supplier Unit Price 1" field and to set a Production Quantity of say 10, or 100 off. This forces Altium to multiply the unit cost by the quantity per board and by the production quantity before rounding! Typically this values is more than 1p and you can get an accurate per board BOM cost by dividing the sum of subtotals by the production quantity.

Of course, this is not perfect, since changing the production quantity can push you into a different supplier price bracket. I'm probably not the first person to find this bug, but because Altium developers keep their bug reporting system private I cannot be sure! I hope to log a bug report as soon as I'm granted a log in to Altium Live.

Hopefully this workaround will be useful to others struggling to calculate a BOM cost for their design.

References:

Altium Wiki page for Live Supplier Links

Update: 27/4/2012

I've registered this as a bug on Altium's Bug Crunch site. You can follow the status here but only if you have an Altium Live account:
http://bugcrunch.live.altium.com/#Bug/1688



Friday, 13 April 2012

Example Sensible Clamz Configuration file

Stick this in your ~/.clamz/config file so that your music gets downloaded to a sensible place with sensible file names. Unfortunately an example config file isn't installed when you install clamz. I had to figure this out from the source code. This might save someone a few minutes of digging around in the future so I've posted it below:

#Sensible Config File for Clamz Amazon MP3 Downloader
#Modified by: http://www.beesnotincluded.com
#Based on options.c from clamz source code

## Clamz configuration file

## Default format for output filenames.  This may contain any of
## the following variables:

##  ${title} ${creator} ${album} ${tracknum} ${album_artist}
##  ${genre} ${discnum} ${suffix} ${asin} ${album_asin}
##  ${amz_title} ${amz_creator} ${amz_asin} ${amz_genre}

## The name format may also contain slashes, if you'd like to
## categorize your files in subdirectories.
NameFormat       "${tracknum} - ${title}.${suffix}"
DirectoryFormat "${album_artist}/${album}/"


## Set to True to allow uppercase in filenames.
## False to convert to lowercase.
AllowUppercase   True

## Set to True to output UTF-8 filenames, False to output ASCII only,\n"
## UseLocale to check the system locale setting.
## Note: Using anything other than ASCII seems to be prone to falling over
## whenever the track name/artist has a hint of french
AllowUTF8        False

## The set of ASCII characters which are disallowed.  (Control
## characters and slashes are always disallowed.)
ForbidChars      "\"!\\\"$*:;<>?\\\\`|~\"

In the future, when you call clamz:
% clamz /tmp/Amazon0123456.amz
You're music will land in the current directory with the directory and file structure specified in the config file.

Saturday, 31 March 2012

You know your circuit analysis has gone wrong ...

...when you're equations look like this:


Original Link: http://a1.sphotos.ak.fbcdn.net/hphotos-ak-ash4/421703_187187921393117_100003057326004_275568_807439304_n.jpg

Saturday, 24 March 2012

Automating VHDL Testbench Creation

I do quite a bit of VHDL development in my job. Most VHDL blocks (entities) that I write are quite short. In my opinion, this is a good thing. It means that you can hold all of the variables in your head at the same time and actually feel confident that you understand how it all works. Smaller blocks are usually easier to reuse. They are also much simpler to test. Having many smaller blocks versus one large block does however mean writing more test benches.  Compounding this additional effort is the fact that VHDL is a very verbose language. My usual approach is to modify a template file which I keep to hand, however this can still take almost as much time and effort as writing the design under test (DUT)!

My goal is to find a better way of writing test benches, so that I can spend more time doing the fun bit, designing the functional design unit! I want to reduce the barrier to setting up a test bench. Ultimately I want to be confident that my design will work before spending time synthesising and testing the design on hardware.

I have found a variety of approaches to automating test bench generation. They seem to fall into the following broad categories:

Test vector based verification

This is the sledgehammer approach. You describe the state of all the input signals for each clock cycle/step of you simulation and then step through each line applying the signals. If you add in assertion statements you can catch errors during simulation. The input test vectors could be a spreadsheet, or generated by hand or by another piece of software. I don't like this approach because it is time consuming, error prone and very hard to read and modify. I can image certain situations where this really may be the best technique, perhaps if you wanted to verify an arithmetic function or a complex checksum calculator.

Transaction based verification

A transaction based simulation relies on using many of the non-synthesisable, sequential features of VHDL to call specific test procedures when certain signal events occur. By using VHDL procedures or components you can write reusable test constructs such as reacting to a read request signal, or the start of a bus transaction. Typically you create a master process which sequences calling each of the processes in turn. You can read more about this in [1] (see sources at end of post). I want to find out more about this style of VHDL and experiment with it to see if it really can expedite the process of writing test benches.

My main concern with this approach is that it requires a completely different style of HDL compared to that which you write when designing the DUT. This makes it quite difficult to switch between writing synthesisable code and writing the testbench. I'm also sceptical because it makes it too easy to forget about how the actual hardware will behave! If your testbench is purely sequential you may end up excluding the consequncies of concurrent events. You may also end up writing asynchronous code which doesn't accurately model the hardware the design under test will be interacting with.

Method 3

This is approach that I take at the moment. I'm not really sure if it has a name. It is simplistic, synchronous and (almost) looks like real, synthesisable VHDL. I typically define a clock and reset as follows:


clk0: process
begin
    Clk <= '0';
    wait for 6 NS;
    Clk <= '1';
    wait for 6 NS;
end process clk0;

rst0: process
begin
    Reset <= '1';
    wait for 12 NS;
    Reset <= '0';
    wait;
end process rst0;

I then set about writing a VHDL module which mimics the behaviour of the hardware which the DUT will interact with. I usually combine this with a counter which I use to synchronise stimulus to the DUT and to get things kick started. The synchronous counter ensures all events happen on active clock edges, as they will in the final design. It also means its easy to add new events to build up the simulation.

Typically I start with a test bench counter:

    -- Generate a test bench counter which we can use to
    -- synchronise events
    process(Clk, Reset)
    begin
        if(Reset = '1') then
            TbCounter   <= to_unsigned(0,8);
        elsif(Clk'event and Clk='1') then
            TbCounter <= TbCounter + to_unsigned(1,8);
        end if;
    end process;


I then generate DUT input signals from the count value:

    -- Example write strobe
    Write <= '1' when TbCounter = to_unsigned(5,8) else '0';

    -- Example address counter
    Address <= std_logic_vector(TbCounter(7 downto 4));

Sometimes it is helpful to capture the outputs of the DUT as they would be by subsequent hardware blocks in the final design. For example capturing a register write:

    -- Implement a storage register to capture the output from the DUT
    process(Clk, Reset)
    begin
        if(Reset = '1') then
            TbRegData   <= X"00000000";
        elsif(Clk'event and Clk='1') then
            if(Write = '1') then
                TbRegData   <= Data;
            end if;
        end if;
    end process;

With these simple building blocks you can set up simulations which exercise the DUT in realistic ways and which make analysis of simulation waveforms straight forward.

Room for improvement

As I mentioned before, writing test benches is time consuming. It is also fairly repetitive. A lot of the information in the DUT has to be replicated in the test bench, such as defining all the i/o signals, wiring up the port map and generating a clock, reset and test bench counter. I have therefore set about automating these initial stages of test bench generation. My end goal is to be able to embed test bench directives in the comments of the DUT port definitions and then run a script to automatically produce a test bench file which is immediately ready for simulation. This can then be used as a starting point for testing the DUT. In many cases, it would probably be all that is required. This is what I have in mind:

entity DUT is
port(
    Clk    : IN std_logic; -- @clk,6250,6250  
    ClkEn  : IN std_logic; -- @clkpulse,1,4,Clk  
    Reset  : IN std_logic; -- @pulse,10000,1,0
    DUTA   : INOUT std_logic_vector(7 downto 0);   -- @static,255
    DUTB   : INOUT std_logic_vector(7 downto 0);   -- @static,0
    DUTOUT : OUT std_logic;                        -- output only
);
end entity DUT;

This would create:
Clk - a clock with the specified high and low times in ps.
ClkEn - a synchronous pulse lasting 1 'Clk' period in every 4
Reset - an asynchronous pulse lasting 10000ps, starting at '1' then transitioning to '0'
DUTA - a statically assigned value of 255 b"11111111"
DUTB - a statically assigned value of 0 b"0000000"

I currently have a script, written in Perl, which performs the following stages:
  1. Creates the entity and architecture statments
  2. Defines all the signals necessary to interface with the DUT
  3. Instantiates the DUT entity and sensibly wires up the port map
I'm working on the next stage: interpreting the '@' directives in the comments and generating the VHDL code required to achieve them. I'm looking forward to publishing it when its more...err...complete?! But for now you can download and run the script on any VHDL file and generate your own test benches. I have tested it on Windows and Linux.

The code is here: http://pastebin.com/0VJJPh95


Please let me know what you think. If you have your own ways of creating test benches I'd look forward to reading them!

Sources:
[1] Manual and Automatic VHDL/Verilog Test Bench Coding Techniques



Sunday, 18 March 2012

MITx

It is week three of the Massachusetts1 Institute of Technology's inaugural on-line course 6.002x Circuits and Electronics. I'm really impressed!
"6.002x (Circuits and Electronics) is designed to serve as a first course in an undergraduate electrical engineering (EE), or electrical engineering and computer science (EECS) curriculum. At MIT, 6.002 is in the core of department subjects required for all undergraduates in EECS." [source]
The course has so far lived up to the high standards expected of an MIT course. I think what distinguishes this course from those at other universities, including Southampton University's excellent ECS School is the effort they have put into making the on-line learning environment (eurgh) as good as possible. The site has been designed from scratch to suit the needs of an electronics course. This includes:
  • On-line access to relevant sections of course textbooks
  • Lectures split into 10 minute videos, all available from youtube
  • Transcripts of all lectures which can be synchronized with the youtube videos
  • Online tutorials with youtube videos showing, and importantly, explaining the worked solutions
  • Proper homework questions with numerical answers which can be checked and graded instantly
  • Virtual electronics labs. They have invested in a browser based circuit simulator which means you can submit circuit diagrams as solutions to questions
I'm really hopeful that MIT will continue to roll out this type of course to cover other electronics, computer science and perhaps even mathematics modules. Furthermore I hope that other universities in England as well as America take note and step up the quality of their on-line course resources. Simple steps as providing relevant sections of the course texts on-line (using something akin to Google scholar to keep the publishers happy) make a big difference. Breaking long lectures into smaller 'chapters' and posting the videos on-line is really useful. You can skip the bits you already understand and rewind to the point where everything stopped making sense.

Although the course has already started you can still enroll here

I have read sections from the course text: Foundations of Analog and Digital Electronic Circuits (The Morgan Kaufmann Series in Computer Architecture and Design). I really like what I have read so far. As first year electronics text books go I think this is the best I've seen. It has a lot of worked examples. Something which is often missing from course texts.



1How many attempts did it take to spell this correctly? Answer: I don't know 'cos I gave up and copied it from the website.

Sunday, 11 March 2012

British Class

The subject of social class has recently piqued my interest. I don't know why it interests me. I wouldn't (although others might?!) describe myself as being class conscious. I certainly don't have well formed opinions on the subject. I can't make up my mind whether it is good or bad, necessary or out-dated or something we should aspire to eradicate altogether.

I started reading an excellent book by the anthropologist Kate Fox titled Watching the English: The Hidden Rules of English Behaviour. In this book she attempts to define a set of rules which underpin the everyday behaviour of the English. What makes this book so good is that instead of just recycling age-old stereotypes and clichés she has undertaken her own social experiments to really test her hypothesis. This includes what must have totalled weeks of observations in various locations and environments ranging from pubs to railway stations. Beyond mere observations some of her experiments included deliberately bumping into people in the street, jumping queues and interrogating confused tourists, baffled by the nuances of English social habits.






Back to class.

Running throughout this book is the omnipresent subject of class. In almost every social situation we seem to have invented ways of classifying people. Kate Fox goes to great lengths to explain the sometimes bizarre and hypocritical indicators of class and status which we are all somehow aware of yet are bound from explicitly indicating or referencing. Kate Fox is obviously not the first person to write about this. Class and the class system is something that writers, reformists, politicians and historians have observed, opposed, debated and interpreted forever. It is this very fact which has got me thinking. Is there really anything British about Class?

To my girlfriends annoyance I've been pondering this recently and something she said really struck me. She is Canadian and she said something along the lines of:
"Of course you get upper/middle/lower classes in Canada but its not like in Britain where its such a big deal"
There clearly is something different about Class or the way it is perceived in Britain compared to North America or Europe and perhaps the rest of the world but what it is? Every society has people at both extremes of the social scale some kind of distribution in between. The nomenclature of upper, lower & middle as class labels translate readily into other cultures so whatever the difference is, it must be more than just the labels we use.

I can see one difference. The wealth of indicators we have in our repertoire for classification and for describing class is vast. One thing which is certain and which Kate Fox points out many times is that class is determined by more than wealth. It is clearly influenced by your parents and personal aspirations. The method of identifying peoples class must therefore be more complicated and detailed. As we've become more cultured, accumulated more material wealth and removed barriers to class entry through schooling and reform it has become harder to identify someone's class. This is not a bad thing. But just having lots of ways of determining someone's class doesn't explain why we as British people care more than anyone else about it (if in fact we do?). Instead it is just another symptom of its importance in society.

It is my suspicion that class matters as much to the rest of the world as it does to the English. Having only ever lived in England I'm not in a position to test this hypothesis! One stumbling point is that the term class is ambiguous, subjective, ill-defined and often read as class prejudice. The definition you use to describe class is itself influenced by your own class! This whole subject is a quagmire!

In this blog and in my head I define class in the mathematical sense as a collection of people with similar properties. This allows for people to have properties which qualify them as members of more than one class.

Melvyn Bragg, broadcaster, social/scientific historian and author has recently presented an excellent three-part documentary series looking at class and culture in Britain over the last 100 years. You can currently watch all three parts on iplayer (geographical restrictions apply): http://www.bbc.co.uk/programmes/b01cmxbb

Saturday, 28 January 2012

Automatically Generate Quartus Pinning From Altium

The task of entering the pin mappings between FPGA I/O pins and signal names is both tedious and prone to errors. FPGA's with 484 pins are pretty common and this is by no means the largest. Typically you will have schematic drawings which you will need to reference to find out which signals are assigned to which FPGA pins. There are rumours that Altium Designer can export pinning information auto-magically however the consensus seems to be that this only works if you use Altium software for both schematic capture and HDL design entry. Since most people use Quartus/Xillinx tools for FPGA development, this is of limited use.

Fortunately, Altium - and just about any other EDA - can reliable export a netlist of you circuit. With this netlist you can readily extract the information you need. That is, the signal name and the FPGA pin number. If you have assigned sensible net labels in your design, it should be possible to convert this netlist file into a tickle script file for use with Quartus. The simplest method of conversion is with VIM text editor

From experience, I've found it best to save your design in the MultiWire (.NET file) format. I'm sure other netlist formats will work but this is the only one I've had success with.

The steps to follow are detailed below:

Step 1:

Open the FPGA schematic sheet(s) in Altium

Step 2: 

Extract a MultiWire Netlist from Altium: Design > Netlist for Document > Multiwire

Step 3: 

Open the netlist file in VIM, You should see a file like the following:

0V                U2                            T1
0V                U2                           T22
1V8               R9                             1
2V5               PL2                            1
2V5               RP36                           2
2V5               RP36                           3
2V5               RP36                           4
3V3               R7                             2
3V3               R8                             2
AUX_IN            U2                            B1
AUXTEST           J1                            11
AUXTEST           TP11                           1
AUXTEST           U2                            D2
CFCD1#            U2                            C3 
 
Step 4: 

Remove all components except the FPGA. You will need to replace "U2" with your chosen designator:

g!/^\p\+\s\+U2\s\+.*/d


Step 5: 

Remove GND, VREF, VCCIO nets (feel free to add more nets to the blacklist):

g/^\(GND\|0V\|1V2\|2V5\|3V3\|FPGAMSEL\|FPGATCK\|FPGATDI\|FPGATDO\|FPGATMS\).*/d


Step 6: 

Convert netlist format to Quartus tickle assignments:

0,$ s:\(\p\+\)\s\+\(U2\a*\)\s\+\(\u\+\d\+\).*:set_location_assignment\tPIN_\3\t-to\t\1


Step 7: 

Check for any reserved pins you might have missed. You can always add these to the blacklist for the next time you use the script.

I have wrapped all of these operations into a single vim function which you can paste into your vimrc file (if you're not sure where this is, type :echo $MYVIMRC).

" Netlist to Quartus tcl assignment file conversion
" Author: http://www.beesnotincluded.com 
" Function: Net2Pin 
" Parameters:
" #1 designator : string : (FPGA) component designator e.g. "U2" or "IC4"
" (case sensitive)
function! Net2Pin(designator)
    "Delete all Nets which aren't connected to specified component designator 
    let pattern = '/^\p\+\s\+' . a:designator . '\s\+.*/d'
    execute  "g!" . pattern
    
    "Delete reserved pins i.e. those used for power/ground/config/jtag
    let pattern = '/^\(GND\|0V\|1V2\|2V5\|3V3\|FPGAMSEL\|FPGATCK\|FPGATDI\|FPGATDO\|FPGATMS\).*/d'
    execute "g" . pattern

    "Convert netlist format to Quartus tcl assignments
    let pattern = '\(\p\+\)\s\+\(' . a:designator . '.*\)\s\+\(\w\+\d\+\).*:set_location_assignment\tPIN_\3\t-to\t\1'
    execute '0,$ s:' . pattern
endfunction 

Once you have saved your changes and reloaded your vimrc file (:source $MYVIMRC) you will be able to call the function as follows:
 
:call Net2Pin("U2") 

Replace "U2" with whatever designator you used for the FPGA in the schematic. The output of this function for the above example is:

set_location_assignment PIN_B1 -to AUX_IN           
set_location_assignment PIN_D2 -to AUXTEST          
set_location_assignment PIN_C3 -to CFCD1#           

License: GNU GPL

References

http://vimregex.com/ - An essential resource for understanding vim regular expressions

:help vim-script-intro - A great starting point for understanding vim scripting

Wednesday, 18 January 2012

The Doobry Lab - Technical Reference App

This is a shameless plug for a colleague's recent venture into Android Application development:

"Nautilus [has been] developed to cover a broad range of technical subjects, without getting too bloated with details. It will never cover any one subject in great detail, but will provide the information most commonly requested at your fingertips."

For more information, visit The Doobry Lab or just go straight to the Android App Store

Monday, 16 January 2012

Vim Foo

My most advanced regular expression to date:

0,$ s:\(\d\+\)\s\+\(\w\+\d\+\):set_location_assignment PIN_\u\u\2 -to HdcSig[\1]

This takes a space-separated-value file of signal names and FPGA pin numbers and generates the tickle assignment statements required by the synthesis tool, Quartus.
Input:
0    aa1 
1    a4
2    b4
3    c9

Output:
set_location_assignment PIN_AA1 -to HdcSig[0]
set_location_assignment PIN_A4 -to HdcSig[1]
set_location_assignment PIN_B4 -to HdcSig[2]
set_location_assignment PIN_C9 -to HdcSig[3]
In Summary it:
  1. Extracts a numeric followed by alpha-numeric field and stores them in \1, \2 variables
  2. Adds a line prefix
  3. Capitalises coordinates
  4. Switches order of signal names vs coordinates
  5. Adds some braces
Result: feeling smug :D

Sunday, 15 January 2012

Peterborough in January

Today we made it to Peterborough (just) to watch the Peterborough Phantoms play the Sheffield Steeldogs in the English Premier Ice Hockey League.

Before the match game, we wondered around Peterborough city. Despite being generally quite ugly, there was one redeeming feature, it's Cathedral. Even on an overcast and freezing afternoon its walled grounds were inviting and its architecture both imposing and impressive. Enough words, here are my favourite photos from the Cathedral grounds.











This one isn't actually of the Cathedral or the grounds. It is the market square in the centre of the town. The sky looked too good to pass up the opportunity to photograph it.

You can view the Picasa album here