Friday, 30 September 2011

Quartus TimeQuest work flow

As part of my long-lasting DDR2 IP block problems I've learned a little about the TimeQuest timing analyser. This is a program included with Altera's Quartus software which provides post-fit timing information about your design. Once the design is synthesised and the fitter has completed, you can run the TimeQuest tool to find out if your design meets the required set-up and hold timings. This is particularly useful/necessary for high speed circuits such as a DDRAM controller.

The TimeQuest tool is not intuitive. It is very powerful and mostly driven by Tickle scripts so I've outlined the design flow which I've come to learn over the past few days.

  1. Compile your design
  2. Launch the TimeQuest Analyser
  3. Create the Timing Netlist - at this step you can specify the speed grade and the temperature model
  4. Read the sdc file, this is the Tickle file containing the design constraints for your design. This may be generated by an IP block or you may have to create this file for your design. It will typically describe the clocks and derived clocks within your project
  5. Update the timing netlist. This step is Really important. I didn't realize this and as a result I found that my timing reports from the compilation stage disagreed with those produced in the TimeQuest analyser
  6. The final step is to source your timing report tickle script. This will present the setup/hold times for your design
If you don't perform step 5, updating the timing netlist, it is possible to find that the timing report produced as part of the compilation stage drastically disagrees with that produced in the TimeQuest analyser - very confusing.

Hopefully this will help anyone else struggling to verify the timing of their design.

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