The TimeQuest tool is not intuitive. It is very powerful and mostly driven by Tickle scripts so I've outlined the design flow which I've come to learn over the past few days.
- Compile your design
- Launch the TimeQuest Analyser
- Create the Timing Netlist - at this step you can specify the speed grade and the temperature model
- Read the sdc file, this is the Tickle file containing the design constraints for your design. This may be generated by an IP block or you may have to create this file for your design. It will typically describe the clocks and derived clocks within your project
- Update the timing netlist. This step is Really important. I didn't realize this and as a result I found that my timing reports from the compilation stage disagreed with those produced in the TimeQuest analyser
- The final step is to source your timing report tickle script. This will present the setup/hold times for your design
Hopefully this will help anyone else struggling to verify the timing of their design.