Thursday, 11 August 2011

Modelsim fail

This isn't a blog post about all the things that I think are wrong with Modelsim, nor about the shortcomings of VHDL as a hardware description language. Instead it is a reminder for me (and possibly others) of what to do for when I see this Modelsim error in the future:


# Fatal error in Process line_78 at C:/.... line 82
# HDL call sequence:
# Stopped at C:/... 82 Process line__78

I wasted about 15 minutes searching the internet for typical causes of this ambiguous error message and searching line 82 for syntax mistakes. In the end I found out that in this case, the 'fatal error' was caused by trying to write a 17bit vector to a register defined as std_logic_vector(15 downto 0) and therefore only 16bits large. I cannot believe that what must be a common mistake was not picked up by the VHDL compiler (not even as a warning) and also not assigned a more descriptive error message. It was only when running the simulation that Modelsim complains.

To reiterate, the following code will generate a fatal error when you simulate it but will probably compile without generating an error:

signal bees : std_logic_vector(15 downto 0)

bees <= X"1234" & '0'; -- 16bits + 1bit = 17bits > length of 'bees'


Daniel R. said...

i hate modelsim.

worst software ever

Anonymous said...

Happened to me too. Very annoying error message. took me like 30 minutes to figure out the solution.