Wednesday, 28 December 2011

Domain name at last

I've finally bought the domain name www.beesnotincluded.com. Links using the old blogspot address will redirect to www.beesnotincluded.com.

Making EE Times more readable

I enjoy reading some of the technical articles on the EETimes website. This is the best site I have found for professional electronic engineers (excluding the IEEE). Unfortunately, reading anything on the EETimes website is excruciating. There are so many adverts and flash videos that even on a fast computer the pages take ages to load, and scroll latency can be measured in minutes. Sadly, this means I quite often put off visiting the site, even though I'm sure there are interesting articles to be found.

Earlier this year I learned about Readability

I downloaded the app and now find reading EET articles far more inviting and a lot quicker. Here is an example of how much of a difference Readability makes

Try reading this:

http://www.eetimes.com/design/test-and-measurement/4227229/Hunting-noise-sources-in-wireless-embedded-systems

Now try making it readable:

http://www.readability.com/articles/bhwlrpmj

I know neither of these concepts are novel, but for anyone else that was put off reading EETimes by its crappy website design, hopefully this might change your mind.

Sunday, 11 December 2011

Replacement sky for overcast photo

Having recently stayed at the magnificent Down Hall I wanted to take a photograph which did the house and its surroundings justice. Unfortunately it was overcast so my photos were all a bit dull. This was the best I could get:


I wanted to do two things. Remove the tissue from the front lawn and replace the sky with one more fitting. Apparently this is trivial in Photoshop, but I only had access to GIMP. So I found this well written tutorial and followed it. After about half an hour of playing around I produced the following result.


It is a little bit rough and I'm not sure the brightness/contrast of the sky matches the photo too well, but I'm pleased!

Sunday, 4 December 2011

Asynchronous behaviour of synchronous counter

I've written before about performing timing analysis with Altera's FPGA design software, Quartus II. I find Analysing timing for a complex FPGA project far from easy. Distinguishing which timing violations are important and which ones are the result of poorly constrained paths can be tricky. Sometimes a path in your design may report negative slack, but you don't care, because you only latch the signal on every other clock, or perhaps because that path's timing just isn't important to your design.

That being said, once you've identified that a timing violation that does concern the performance of your design it can be tricky to understand what the Timing Analyzer is saying. Typically all you have to go on is a source and destination 'node' in your design and the corresponding clock domains to which the violation concerns. Earlier this week I came across a timing violation which at first glance didn't make any sense.

The analyser flagged a negative slack time from the q[] output of a counter (marked as 'source') to the register 'reg' marked as 'dest' in the diagram below:



This didn't make any sense. There is no combinational logic joining the source to the destination. At least it looks that way on first inspection.

If you consider the behaviour of the synchronous counter, the cout output is dependent upon the direction of the counter. When counting upwards, cout goes high when the counter value is '1111..11' however when counting down, cout goes high when the count reaches '0000...00'. This implies that cout is  directly, and combinationally dependent upon updown.

The reason for the timing violation now makes sense, the combinational path joining source to dest now includes 'path_a' and 'path_b' in series, it is as if the path continues from the updown input through to cout output of the counter.

This path includes quite a lot of combinational logic, hence the failure to meet timing requirements. It is these sorts of subtleties that make resolving timing issues far from trivial.

Source: "lpm_counter Megafunction User Guide", Altera, 2007, retrieved 4th December 2011, URL: http://www.altera.com.cn/literature/ug/ug_lpm_counter_mf.pdf

Thursday, 27 October 2011

Excel can't do maths

I stumbled upon a little publicised bug in the current version of Excel whereby it displays the wrong trend line equation on scatter graphs.

http://support.microsoft.com/kb/114629

You would expect such a simple and often used function to work but apparently not. I only discovered this after someone tried to use the equation I'd presented to them and complained that it was wrong!


The lesson I've learned is to always double check my maths, regardless of whether I had 'help' from a computer.

Friday, 30 September 2011

Quartus TimeQuest work flow

As part of my long-lasting DDR2 IP block problems I've learned a little about the TimeQuest timing analyser. This is a program included with Altera's Quartus software which provides post-fit timing information about your design. Once the design is synthesised and the fitter has completed, you can run the TimeQuest tool to find out if your design meets the required set-up and hold timings. This is particularly useful/necessary for high speed circuits such as a DDRAM controller.

The TimeQuest tool is not intuitive. It is very powerful and mostly driven by Tickle scripts so I've outlined the design flow which I've come to learn over the past few days.

  1. Compile your design
  2. Launch the TimeQuest Analyser
  3. Create the Timing Netlist - at this step you can specify the speed grade and the temperature model
  4. Read the sdc file, this is the Tickle file containing the design constraints for your design. This may be generated by an IP block or you may have to create this file for your design. It will typically describe the clocks and derived clocks within your project
  5. Update the timing netlist. This step is Really important. I didn't realize this and as a result I found that my timing reports from the compilation stage disagreed with those produced in the TimeQuest analyser
  6. The final step is to source your timing report tickle script. This will present the setup/hold times for your design
If you don't perform step 5, updating the timing netlist, it is possible to find that the timing report produced as part of the compilation stage drastically disagrees with that produced in the TimeQuest analyser - very confusing.

Hopefully this will help anyone else struggling to verify the timing of their design.

Misleading Quartus Messages

For the last few weeks I've been struggling to get a closed source IP block from Altera to work. The block is a DDR2 controller for the Cyclone IV range. As part of my debugging I scrutinised all of the Quartus Analysis & Synthesis info and warning messages to try to get to the bottom of the problem (which is still unresolved). One message which stood out was the following:

Info: Instantiated megafunction "Ddr2RamController... with the following parameter:

      Info: Parameter "intended_device_family" = "Cyclone III"

...

Info: Instantiated megafunction "Ddr2RamController... with the following parameter:

      Info: Parameter "intended_device_family" = "Cyclone IV E" 
 
The compiler appears to instantiate some of the Megafunctions for the Cylcone III (which is different from the target device) and some for the Cyclone IV.

I subsequently highlighted this in a service request to Altera.

The official response from Altera is that this is the correct behaviour - despite being incredibly misleading. It turns out that the intended_device_family parameter is only used for simulation purposes, so the fact that it doesn't match the target device is irrelevant. Furthermore the altera docs (PDF page 55) does not allow for this parameter to be set to "Cylcone IV" - presumably, the IP block should behave identically in the Cyclone IV as it does in the earlier Cyclone III.

The result for me is that I'm still no closer to solving my DDRAM issues.

Hopefully this information will prove helpful to others struggling with misleading Quartus info/warning messages.

I originally posted a query about this in the Altera Forums to no avail:

http://www.alteraforum.com/forum/showthread.php?p=129172#post129172

Friday, 23 September 2011

Big Dog

A friend at work informed me of this US DARPA funded project called Big Dog. Watch the video of this robotic dog in action:

It is made by a US company called Boston Dynamics and they have published some slides and a technical paper about the different technologies and the use of compliant materials within the robot. I'd hate to think what the R&D costs of something this advanced would be. The Big Dog project website has links to the aforementioned presentation and technical paper. My favourite part of the video is when they kick Big Dog on the ice and it stumbles briefly before recovering. The slow motion jumping sequence is very impressive too!

Sunday, 18 September 2011

Holiday themed quiz

As part of our Canadian Thanksgiving celebrations we wrote a holiday themed quiz. Topics range from bizarre holiday customs through to holiday foods and films. The questions, and answers, can be downloaded here:

Holiday Questions

Holiday Answers


If you liked this you may also like:
  1. Canadian Quiz
  2. Thanksgiving Quiz Latex Template
  3. Pork Timing Diagram

Pork Timing Diagram

In preparation for a big Canadian thanksgiving dinner I prepared an ever so slightly nerdy timing diagram for cooking all the ingredients. I started off with the intention of a drawing a Gantt chart but several weeks of staring at DDR2 ram data sheets must have had an effect! The result was remarkably clear and the food turned out O.K so I'd call that a success!

Sunday, 11 September 2011

PDF Forms are Evil

I have to fill out some government forms which are all interactive PDF forms. Some of them even have the ability to save the form data deliberately disabled:


I cannot believe someone at Adobe thought this a good idea. I don't have a printer, so it means printing the stupid form to a postscript file! This doesn't smell like progress to me?

PDF forms are bad for other reasons too. They only seem to work properly with Adobe's PDF reader, so fat chance of using evince for linux or any other open source reader. Even after installing Adobe Reader for linux (shudders) the form is so unusable that you really have to question what the point of them is?

So in conclusion PDF forms are evil.

Saturday, 10 September 2011

A long weekend in Copenhagen

Copenhagen is a beautiful city and Danes are lovely people.

We recently spent the British August bank holiday in Copenhagen. Arriving early on the Friday morning after an uncomfortable Easyjet flight from Stansted we disembarked in glorious sunshine. Copenhagen airport is, like the rest of Copenhagen, beautifully designed, terrifically efficient (average time through security: 6 minutes) and welcoming. The newly built and still expanding metro service (which incidentally is suicide proof!) takes you straight from the terminal to the city centre in under 15 minutes and for not many Kroner. And from the city centre just about everything is within walking distance.

I'm no travel writer so here is a photo illustrated list of my prevailing thoughts and impressions of this magnificent city:

Copenhagen has a lot of parks and public gardens. You can spend a day just walking around parks if you wanted to. Locals seem to use them too. When the weather was good we saw Danes pitched in parks with crates of Carlsberg/Tuborg. Below is the most beautiful of all the parks, the Botanic Gardens:

From Copenhagen, Summer 2011


Danes do design. The state museum for modern design is a good example of this. I just wish my photography could do it justice:

From Copenhagen, Summer 2011


Even the children's play area is stylish and 'designed':

From Copenhagen, Summer 2011


Herons are a common site in the many parks and gardens. So much so there are statues of them dotted around the city:

From Copenhagen, Summer 2011


These terracotta buildings used to be army barracks but they seem to be domestic dwellings nowadays. I thought they looked stunning and enjoyed photographing them:

From Copenhagen, Summer 2011


From Copenhagen, Summer 2011


This windmill resides at the centre of an active fort, surrounded by a star-shaped moat:

From Copenhagen, Summer 2011


There is a _lot_ of graffiti in Copenhagen, this was one of the less permanent examples:

From Copenhagen, Summer 2011


Danes love their statues. Below is the famous Little Mermaid statue, a frequent victim of political activists. Below that is a statue we found en route which we mistook for the little mermaid. I'm divided as to which one I prefer:

From Copenhagen, Summer 2011


From Copenhagen, Summer 2011


We came across some crazy Danes. Here are some of them:

From Copenhagen, Summer 2011


From Copenhagen, Summer 2011


From Copenhagen, Summer 2011


Just about every famous Danish person in history was called Christian. Here is the city's much loved Hans Christian Anderson, children's author and figurehead for the city:

From Copenhagen, Summer 2011


Copenhagen is a city of canals. This one completely separated the state offices from the mainland. It was frequently circumnavigated by tourist barges not much smaller than the archways of the many bridges that cross it.

From Copenhagen, Summer 2011


From Copenhagen, Summer 2011


Back to more striking architecture and this is the new university library. Its like a glass battleship beached along the canal. Inside it has expansive concrete balconies and stairways at inconvenient angles, curvy passageways and a pretty reasonable cafe.

From Copenhagen, Summer 2011


From Copenhagen, Summer 2011


Christiania is an odd place. It is a self ruling community established in the seventies at a disused military base. It is now a haven for soft drug users, hippies and graffiti artists seeking something approaching immunity from the law. It is a surprisingly popular tourist destination. You are prohibited from running and taking photographs - both activities 'make people nervous'. Below is the entrance to this place.

From Copenhagen, Summer 2011


If you want a beer in Copenhagen you have a choice of Carlsberg or Tuborg. Both are now brewed by Carlsberg brewery and it could be argued are indistinguishable. Drinking out is not cheap in Copenhagen. Even though the brewery is a stone throw from the centre. We took a S-train out of the city to visit it. There is a quaint museum charting the history of brewing in Denmark and an impressive, world record breaking, collection of bottled beer.

From Copenhagen, Summer 2011


From Copenhagen, Summer 2011


As part of the preparations for our visit I compiled a Google map with markers of all the places to visit. Since I don't have a camera with geo-tagging capabilities (yet) I've embedded the map below so I can remember where we went and what we saw (and photographed):


View Copenhagen Trip Aug '11 in a larger map

All my photos from this trip are in this Picasa web album:

99% Invisible

Its not often that I find a blog which interests me so much that I want to link to it. 99% Invisible is one of them.

It is a collection of well produced, succinct podcasts about design, architecture and engineering. Some of my favourite episodes cover topics such as:

Redesigning the bank statement

Samuel Plimsol's eponymous line

The Great Pyramids

Saturday, 20 August 2011

Advice for PCB assembly

At work I've been developing two new PCBs. These are both eurocard size boards with a high component count and some tricksy BGA and QFN parts. For prototype builds we typically use an external company to assemble the boards. I've been through the process of getting boards assembled several times before, but this current project is by far the most complex and the assembly process has been far from straight forward.

A three working day quote turned into a six day turn-around. Consequently, I've learned a few things about how to manage this process and I want to share what I have learned.

Lesson #1 Make the assembler's life as easy as possible. If you don't, they will make your life as hard as possible. An extra couple of hours of your time spent preparing the data files will speed up the build, reduce the number of component placement mistakes and curry favour with the assembler.

Lesson #2 Supply good assembly drawings. CAD programs are really good at auto-generating this kind of output, but left unchecked they will produce accurate but unhelpful drawings. A good assembly drawing will be a PDF showing each component layer (separately) and all the component designators for that layer. If the board is very compact, enlarge the print so it is more than just a 1:1 print. Use layer colours which are easy to read and which have high contrast.

For prototype builds, it is very unlikely that an assembler will use a pick and place machine to populate the board. It just isn't worth their time. Unless you are supplying parts on reels, the time taken to re-reel components and load the machine is crazy. This means your boards will be placed by hand and so providing clear, human readable drawings is essential.

Lesson #3 Carefully prepare the components This is mainly common sense. If you are getting multiple boards assembled, keep the parts for both in separate boxes. Order spares of inexpensive components. An extra few pounds spent on passive components is preferable over having to leave them off the board or delaying the build to buy more. If you order your components from Digikey, during the checkout process you can enter the component designators corresponding to each part. These will be printed (space permitting) on the component bag label when your order is prepared. This makes it much quicker to find components.

Lesson #4 Check the BOM carefully Again, this is pretty much common sense. Make sure that any no-fit components are removed from the BOM. Failing to do this can mean the assembly is delayed while they look for the missing parts.

Lesson #5 Keep track of your changes This one really caught me out. It is common to purchase components as soon as you have the first draft of the schematic ready. This means you have time to sort out long lead time components while you are revising the design. Inevitably, changes will need to be made to the BOM after this initial order has been placed as issues are discovered during the review/layout stages. If you don't keep track of these changes and order the new parts you will have problems during assembly. One method is to compare the first BOM with the final BOM and spot the differences, but this is tedious and prone to error. It is better to generate an Engineering Change Order (ECO) for each of the changes as you make them. This can be a simple spreadsheet listing the designators affected and the nature of the change. This may sound time consuming but it will save you a lot of lost time later on.

Lesson #6 Get progress updates It is worth checking in on the assembly process every couple of days. A short phone call to check everything is going O.K. may help you spot and resolve parts queries/shortages before they add half a day's delay to your project.

Lesson #7 Remember its a prototype I think most assembly companies acknowledge that during prototype builds there will be problems with the BOM and the odd component shortage. From my experience, they are happy to put the build aside for a day while you fire off a Farnell order to get hold of the missing parts.

This may all seem pretty obvious, but in the hurry to get your prototypes made and meet your next milestone, it is easy to let some of these points slip.



Thursday, 11 August 2011

Modelsim fail

This isn't a blog post about all the things that I think are wrong with Modelsim, nor about the shortcomings of VHDL as a hardware description language. Instead it is a reminder for me (and possibly others) of what to do for when I see this Modelsim error in the future:



Reprinted:

# Fatal error in Process line_78 at C:/.... line 82
#
# HDL call sequence:
# Stopped at C:/... 82 Process line__78
#

I wasted about 15 minutes searching the internet for typical causes of this ambiguous error message and searching line 82 for syntax mistakes. In the end I found out that in this case, the 'fatal error' was caused by trying to write a 17bit vector to a register defined as std_logic_vector(15 downto 0) and therefore only 16bits large. I cannot believe that what must be a common mistake was not picked up by the VHDL compiler (not even as a warning) and also not assigned a more descriptive error message. It was only when running the simulation that Modelsim complains.

To reiterate, the following code will generate a fatal error when you simulate it but will probably compile without generating an error:

signal bees : std_logic_vector(15 downto 0)

...
bees <= X"1234" & '0'; -- 16bits + 1bit = 17bits > length of 'bees'


Saturday, 2 July 2011

Canada Day

Friday 1st July was Canada day, which reminded me about last year's Canadian Thanksgiving quiz which I never got around to uploading, despite blogging about the LaTeX foo I used to make it. Well here it is, for anyone who wants to test their knowledge of Canadian geography, history, sports and celebrities.

Here are the questions

Here are the answers

Happy Canada Day!

Saturday, 21 May 2011

Inductor selection for Switch Mode Supplies

Recently at work I have had to design a few switch mode power supply circuits. I haven't had too much experience at designing these before and have so far got away with following recommended circuit topologies in the switcher datasheet. This has generally worked out O.K. but you can end up with an over-specified inductor which has many implications for the performance of the final circuit. Another problem with this approach is that blindly trusting the manufacturers datasheet examples is bound to lead to problems eventually. The design criteria for such circuits are rarely specified beyond output voltage/output current, there is no mention of ripple current/voltage, overshoot, power dissipation...

I set out to get a better understanding of how switch mode power supplies work, and understand the equations which underline their performance. This post is a collection of the resources I found during the learning process.

My starting point was SMPS Technology which has a short tutorial on the basics of switching regulators. This outlines the basic inductor equations and how to apply these to a buck regulator. It offers suggestions on choosing suitable inductor and capacitor values based on simple 'rules of thumb'. Helpfully, it explains the different approaches to controlling switch mode supplies and the effects of each method on stability and overshoot.

Having read this tutorial through a few times, I was keen to understand where these rules of thumb had come from and what the implications of following them were. After a trawl of switching regulator manufacturer's websites, I came across a National Semiconductors Application Note 1197. This is an expertly written document which explains how to select an appropriate inductor for your application. As well as showing how to choose a starting value for your inductor, it explains how to calculate the RMS current, Peak current, energy handling capability and saturation current required for you application. Furthermore, it shows how you can take the parameters from an Inductor datasheet and calculate the power losses due to core losses and copper losses and therefore work out the temperature rise.

Another good resource for selecting an Inductor is the Coilcraft website. Their Inductor Selector for DC-DC converter circuits is a pretty good starting point. Once you have chosen an inductor, they also provide an inductor loss calculator.

If you want to be even more lazy you can try the National Semiconductor WEBENCH tool, which will not just select an inductor but will design the whole switch mode circuit for you, including sourcing all the components! I tried using this for the last switch mode circuit I designed to see how good it was. I was sceptical that it would do a good job. The circuit topology it suggested was pretty much the one from the datasheet with some important exceptions. It suggested an output capacitor with a large ESR which would have given poor voltage ripple. It violated the maximum resistance for the feedback resistors and it missed of the soft start capacitor. In conclusion, don't trust it to get everything right just yet!

Monday, 16 May 2011

Farnell Box Ticker

Frequent users of the Farnell website may, like me, get annoyed at having to continually tick the 'in stock', 'RoHs' and 'Exclude extended range' check boxes while searching for parts. Unfortunately, these check boxes do not seem to stay checked beyond a single search, even if you log in it will not save your preferences.

Using Greasemonkey to tick Farnell Search Boxes



So I set about writing a greasemonkey script to automatically tick these boxes when the page loads. Just in case I later decided I did want to pay £16 to ship a resistor across the Atlantic, I decided to add a keyboard short cut to invert the selection.

It turns out that greasemonkey is really annoying. User scripts execute in a sandbox, which means you can't access elements on the page or in the DOM as you would in say Firebug or a script running on the page itself. There is quite a lot of documentation out there about all these quirks, but even simple things like changing the value of a checkbox becomes a real headache.

After spending an evening getting to grips with Greasemonkey and refreshing my Javascript foo, I thought I had it cracked. So much so that I uploaded my efforts and boasted about it on Twitter. Then I took a closer look and discovered that all my script actually achieved, was graphically ticking the boxes on the Farnell search page and not actually affecting the search.

A little more time spent inserting breakpoints into the Farnell application script and I found the function that needed to be called to affect the search. For this, Firebug was essential! From the DOM tab, you can right click on an element and select 'Break on attribute change'.

Installing the script


The working script can be downloaded from userscripts, it is called: Farnell Box Ticker or you can directly install it by clicking this link

Unlike many scripts, this does not use the potentially unsafe 'Unsafe Window' work-around. Instead it relies on the fact you can type javascript directly into the URL box in your browser like thus: javascript:alert('beesnotincluded"');


Using the script


Once installed, this script will run on all of the farnell domains (hopefully). On the non-parametric search pages, the Stock,ROHS,Extended items boxes will automatically be ticked. For parametric searches, these boxes cannot be automatically ticked, because they are generated dynamically after the page has loaded. You can however, use the CTRL+E shortcut to toggle the state of these boxes on these pages.

Bug reports welcomed :s

Thursday, 28 April 2011

Alternatives to amazon downloader

I'll keep this short, because I've just spent in excess of an hour trying to get Amazon's official, propitiatory downloader for linux Fedora 13 to work. The problem is that Amazon's binary is dynamically linked to old versions of C++ Boost libraries which are not part of Fedora 13 or beyond. Trying to install the old libraries and all their dependencies is a nightmare.

The solution is Pymazon. It works, its open source, its python (so installing it is a child's play) and best of all it is better than Amazon's official offering.

Also Clamz exists but I've not used it so cannot vouch for it.